1. Field of the Invention
The present invention relates generally to a semiconductor technique and more particularly to a silicone-containing dielectric film having good mechanical strength.
2. Description of the Related Art
In the plasma chemical vapor deposition (plasma CVD) method, a film is formed on a semiconductor substrate by placing the semiconductor substrate, being the processing target, on a heater of resistance heating type, etc., that has been heated to a temperature of 0 to 350° C. in an atmosphere of 1 to 10 Torr. The heater is installed in a manner facing a shower plate that releases a reactant gas, and RF power of 13.56 to 60 MHz, etc., is applied to the shower plate at an output of 100 to 4,000 W to implement RF discharge between the heater and shower plate and thereby generate plasma. This plasma CVD method is used to form thin films such as inter-layer insulation films, passivation films and anti-glare films.
Since causing an excessive surface diffusion is difficult in plasma CVD processes of parallel plate type, traditionally oxide films and other films having embedding characteristics have been used in high-density plasma CVD processes using microwaves. For copper wirings adopted for the purpose of improving RC delays, the damascene technology whereby grooves are formed in an insulation film to embed copper was adopted to address the difficulty associated with etching of copper materials. Adoption of damascene structures eliminated the need to require insulation films to provide embedding characteristics and height-gap covering performance, and at the same time low dielectric constant films were adopted for the purpose of lowering the dielectric constants of insulation films. Low dielectric constant films were adopted first by logic devices having a node of 90 nm, which are currently mass-produced using films with a dielectric constant of approx. 3.0 to 3.3.
Manufacturers are developing low dielectric constant films in response to the need for films having a dielectric constant of 2.5 or less at device nodes of 45 nm and less. However, lowering the dielectric constant promotes density reduction, resulting in the film sustaining significant damage in the etching, ashing and other steps in the damascene process. The various damages sustained in these steps cause the dielectric constant of the low dielectric constant film to increase by approx. 0.1 to 0.5, which reduces the benefit of using the low dielectric constant film in the first place. In view of the above, sometimes a step to restore the dielectric constant using the restore technology is combined to restore the damaged film. At device nodes of 32 nm and less, however, low dielectric films having even a lower dielectric constant are needed, where the required dielectric constant is around 2. A dielectric constant of 2 can be achieved by increasing the amount and size of voids formed in the film. However, it lowers the film density too much and causes the film's resistance to the damascene processing technology to deteriorate significantly. Since conventional methods for forming low dielectric constant film increase the amount of voids in the film while also enlarging the void diameter to achieve the required dielectric constant levels, there is a trade-off relationship between these methods and film density.
As low dielectric constant films using silicon materials, SiBN containing boron (B), and BN, BCN and other films having boron in their basic composition, are evaluated. Although these films achieve a dielectric constant of 2 or even less, inclusion of boron in the composition presents concerns over insulation performance. In particular, these films tend to lose resistance over time. To avoid these problems, oxidization of B must be prevented. Since the film composition significantly affects the degree of oxidization of B, the correlation of film composition and reduction of dielectric constant must be investigated.
To control the dielectric constant in the formation of a low dielectric constant film, the diameter and amount of voids formed in the film are adjusted. As voids generate, the density of the film decreases while its mechanical strength also drops. Conventional silicon oxide films used in wiring processes had a density of approx. 1.9 g/cm3 and a modulus of 50 GPa or more, which made them high quality films. On the other hand, the dielectric constants of low dielectric constant films adopted by 90-nm node devices are approx. 3.0 to 3.3, and their film density and modulus are approx. 1.4 to 1.6 g/cm3 and approx. 20 to 30 GPa, respectively. Significant changes to the processing schemes using conventional silicon oxide films increased the time needed to start mass production, because improving the processing scheme to prevent damage caused by lower mechanical strength took longer than anticipated. However, such problems have since been resolved and prototypes and production devices of 65, 45 and 32-nm nodes are currently produced.
As for 65-nm node devices, in many cases films having dielectric constants equivalent to those of films used with 90-nm node devices are employed as insulation films between copper wiring layers. This is mainly due to the fact that an extra time is needed to evaluate the processing if low dielectric constant films having different dielectric constants are used for each generation of devices, and also to the discovery that the required dielectric constants can be amply achieved by lowering the dielectric constants using silicon carbide films used for prevention of copper diffusion. Actually dielectric constants have been dropping since 45-nm node devices, which are adopting films having a dielectric constant of approx. 2.5 to 2.8. Here, EB, UV and other types of curing technologies are used to prevent the film from being damaged due to the processing technology, to improve the density and mechanical strength of the film.
Starting from 32-nm node devices, the required levels of dielectric constant have suddenly dropped to a range of 2.0 to 2.2. The film characteristics of low dielectric constant films are notably different between the generations before and after. In particular, aging caused by leaving the formed film in the environment presents a critical problem. Pre-processing steps must be controlled to prevent this aging, which also gives rise to problems associated with complex handling. The first step implemented after a low dielectric constant film has been formed is to form via holes and trenches by means of dry etching. Thereafter, ashing is performed to remove residues, followed by chemical rinsing. A film damage occurs when the carbon contained in the low dielectric constant film dissociates due to the plasma used in dry etching and ashing and the film is permeated by the chemical solution used in the subsequent process. This permeation of chemical solution increases the dielectric constant of the low dielectric constant film by a significant margin of 0.2 to 0.5. When the film is let stand for 3 days thereafter, the dielectric constant will eventually exceed 10. As a result, the insulation characteristics will be affected and the insulation resistance will drop significantly.
Under the conventional methods, the porogen technique, whereby voids are removed from the formed film via curing, is generally used to reduce the low dielectric constant with ease. The increasing trend is that the control after void generation depends mainly on porogen material and curing. On the other hand, many problems remain unresolved regarding the controllability of film quality and stability associated with use of porogen material, because porogen residues in the film present problems.